Multi-technologies on-chip interconnects for manycore architectures

This job offer has expired

    Université de rennes - IRISA
    Computer scienceInformatics
    EngineeringElectronic engineering
    First Stage Researcher (R1)
    Recognised Researcher (R2)
    Established Researcher (R3)
    Leading Researcher (R4)
    07/06/2019 00:00 - Europe/Brussels
    France › Lannion


Since few years we are witnessing the emergence of manycore architectures, namely to the implementation of massive parallelism on a single chip. Associated with the shrinking size of the transistors, announced reaching an 11nm technology on 2020, these manycore architectures should reach the integration of thousands of heterogeneous cores allowing huge parallel computation capabilities suitable for High Performance Computing (HPC) and embedded systems.

These parallelism capabilities obviously generate an enormous amount of data exchanges making the communication medium a key element of the overall performance of the system. Massively parallel manycore architectures are showing the scalability limits of electrical NoCs (ENoCs) that suffer when facing thousands of cores. This generates an increase in the latency, hence in the power consumption. Theses degradations are also amplified while the size of the wire decreases.

Technology evolution has allowed for the integration of silicon photonics and wireless on- chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. The recent publications highlight advantages and drawbacks for each technology: WNoCs are efficient for broadcast, ONoCs have low latency and high integrated density (throughput/cm2) but inefficient in multicast, and ENoC still efficient for average size of NoC. In this context, this project proposes to associate these three technologies. Each NoC technology possesses particular and complementary advantages allowing to efficiently route messages depending on their profile: short or long distance, uni- or multi-cast.

The main objectives of this thesis are

Defining a Scalable Hybrid NoC (SHNoC) associating electric, optic and wireless communication NoCs to take advantage of each technology;

Provide adaptive Quality of Service by efficiently routing the messages on the most efficient technology with respect to application constraints (e.g. minimizing energy, respecting latency, etc.).

Main activities

The thesis works will be organized regarding the following activities:

The first activity consists in the study of the state of the art in recent advances for each on-chip interconnect technology. This study will allow to identify the process compatibilities and the physical possibilities or limitations of association (e.g. number of antennas that is physically possible to implement on a specific chip size).

The second activity is the characterization of communication models (energy, throughput, latency) for each NoC technology. The aim is to define high level models to integrate them in a manycore simulator (e.g. NoXiM) in order to evaluate communication performance on real life benchmark.

Regarding the last activity, we will propose routing protocols to provide a Quality of Service (QoS) to the application by targeting a minimal energy consumption, or latency. This routing protocol will define, regarding the targeted QoS and the message profile, the path among the hybrid interconnect.

Offer Requirements

Specific Requirements

Master student in computer science;

Knowledges and skills in:

  • embedded digital architectures, parallel computing; 
  • coding in SystemC, C++, Python, VHDL/HLS, Matlab

Knowledge in on-chip interconnects, and in optical and wireless communications is a plus but is not mandatory.

Work location(s)
1 position(s) available at
Université de rennes - IRISA

EURAXESS offer ID: 409274
Posting organisation offer ID: 85553


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